`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    12:07:40 04/20/2009 
// Design Name: 
// Module Name:    equality_det 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module equality_det(in1, in2, out,clk);
    input [31:0] in1;
    input [31:0] in2;
    output out;
	 input clk;

wire[31:0] wire1;

reg out;

assign wire1 = in1 ~^ in2;

always @ (negedge clk)
begin
	if(wire1 == 32'b11111111111111111111111111111111)
		out = 1'b1;
	else
		out = 1'b0;
end
endmodule
